Silicon carbide semiconductor switching device

ABSTRACT

The present semiconductor switching device comprises a silicon carbide single crystal of hexagonal symmetry having a first conductive type and a semiconductor region of a second conductive type opposite to the first conductive type and locating in the silicon carbide single crystal. The silicon carbide single crystal of the first conductive type and the semiconductor region of the seconductive type form a pn junction. The pn junction interface has an interface extended in the depth direction from the surface of the silicon carbide single crystal, and the interface includes a crystal plane in parallel to the &lt;11 2 0&gt; orientation of the silicon carbide single crystal or approximately in parallel thereto, thereby reducing the leak current.

TECHNICAL FIELD

The present invention relates to a semiconductor switching device usingsilicon carbide.

BACKGROUND ART

Silicon carbide (SiC) has been now regarded as an important material forsemiconductor switching devices applicable to circumstances to whichsilicon is hardly applicable or semiconductor devices with suchproperties that silicon cannot attain.

Silicon carbide has a band gap about three times as large as that ofsilicon and thus is applicable to considerably higher temperatures thanthe application limit temperature (150° C.) of silicon. Furthermore,silicon carbide has a larger dielectric breakdown voltage, e.g. largerby approximately one order of magnitute, and thus can reduce theresistance of a power semiconductor device designed for constantvoltage-withstand to one-tenth or less than that of silicon device.

These distinguished properties of silicon carbide are all due to a verystrong bounding force between carbon and silicon in the silicon carbidecrystal, which, on the other hand, brings about various problems inprocesses for forming semiconductor devices, though.

For example, in case of forming a semiconductor region ofcounter-conductive type on parts of p- or n-type semiconductor crystalsubstrate surface, a diffusion process is usually used in case ofsilicon, but in case of silicon carbide the diffusion rate of impurityelements in the crystal is very low because of the strong bonding andthus the diffusion process, when applied to silicon carbide, willrequire high temperatures such as 2,000° C. or higher and a longprocessing time, rendering its practical application substantiallyimpossible. In case of producing a semiconductor device based on siliconcarbide, the so called ion implantation process is used, which implantsions of necessary elements for forming a semiconductor region throughopenings of a mask coated on a semiconductor crystal substrate surfaceunder an acceleration voltage of a few tens to a few hundred kV, asdisclosed in JP-A-6-151860.

However, in the ion implantation process, many defects are introducedinto the crystal during the implantation, causing another problem. Toimprove the defects and activate impurity elements in the implantedlayer, a heat treatment is usually carried out. In case of siliconcarbide, the heat treatment is carried out at high temperatures e.g.1,400° C. to 1,700° C. but, as disclosed, for example, in SiliconCarbide and Related Materials 1995 (Proceedings of the SixthInternational Conference), p. 513, many defects still remain even afterthe heat treatment. The residual defects are a cause of leak currentwhen an inverse voltage is applied to the pn junction of a semiconductorswitching device based on silicon carbide.

DISCLOSURE OF THE INVENTION

The present semiconductor switching device comprises a silicon carbidesingle crystal of hexagonal symmetry having a first conductive type (p-or n-type) and a semiconductor region having a second conductive typeopposite to the first conductive type and locating in the siliconcarbide single crystal. A pn junction is formed between the siliconcarbide single crystal of first conductive type and the semiconductorregion of second conductor type. The pn junction interface includes aninterface extended in the depth direction from the surface of siliconcarbide single crystal, and the extended interface includes a crystalplane in parallel to the <1120> orientation of silicon carbide singlecrystal or approximately in parallel thereto, where the underline givenbelow the orientation index “2” has the same meaning as that of “−”given above the index in the conventional crystallographic rotation. Aswill be described later, in the semiconductor region of secondconductive type, crystal defects formed on the crystal plane in parallelto the <1120> orientation or approximately in parallel thereto with adeviation therefrom within an angle of a few degrees are smaller in sizethan those formed on other crystal planes, and thus the leak currentdensity generated on the crystal plane in parallel to the <1120> orapproximately, in parallel thereto is lower than that generated on othercrystal planes. That is, the inclusion of the crystal plane in parallelto the <1120> orientation or approximately in parallel thereto in the pnjunction interface can reduce the leak current in the semiconductordevice based on the silicon carbide single crystal.

Having made detailed observations of defects remaining in the siliconcarbide single crystal after the introduction of impurity by ionimplantation, etc., the present inventors have newly found in that thedefects in the hexagonal silicon carbide single crystal were in thefollowing states: observations from different directions ofcross-sections of impurity layer formed in the silicon carbide singlecrystal revealed that the state and distribution of defects as observeddiffered from one direction to another and the defect size was largerwhen observed from the <1120> orientation of crystallographicorientation index of silicon carbide single crystal, whereas the defectsize was smaller or substantially unobservable, when observed from the<1100> orientation.

FIG. 1(a), (b) and (c) are structural views showing the respectivecrystal planes {0001}, {1100} and the respective orientations <1100> and<1120> in unit lattice of hexagonal silicon carbide single crystal,where the orientations <1100> and <1120> are perpendicular to the planes{1100} and {1120}, respectively. Angle of the <1120> orientation to the<1100> orientation is 90 degrees or 30 degrees.

It is preferable that a proportion of the crystal plane in parallel tothe <1120> orientation of silicon carbide single crystal orapproximately in parallel thereto, which is included in the pn junctioninterface extended in the depth direction from the surface of siliconcarbide single crystal, is larger. According to the present inventions'study, it is preferable that the proportion is larger than a half of theentire interface extended in the depth direction from the surface ofsilicon carbide single crystal at the pn junction interface.

The present invention is applicable to such a semiconductor switchingdevice having a pn junction that a depletion layer is extended from thepn junction in a working state or a blocking state. Furthermore, thepresent invention is also applicable to a semiconductor switching devicehaving a pn junction for injecting carriers into the semiconductorswitching device. In that case, the present invention is effective forimproving the carrier injection efficiency at the pn junction andreducing the on-state voltage or power loss of the semiconductorswitching device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is structural views each showing crystal planes and crystalorientations in the unit lattice of hexagonal silicon carbide singlecrystal.

FIG. 2 are a perspective view and a plan view of a junction-gate fieldeffect transistor, respectively, according to the present invention.

FIG. 3 is a perspective view showing the state of crystal defects in thegate layer of the junction-gate field effect transistor of FIG. 2, andits plan view.

FIG. 4 is cross-sectional views each showing only the pn junctioncomprising a drift layer and a gate layer, respectively, in FIG. 2 andFIG. 3.

FIG. 5 is a distribution diagram of leak current at pn junctions formedin the SiC single crystal.

FIG. 6 is a perspective view and a plan view showing a junction-gatefield effect transistor, respectively, where the pn junction interfaceis in parallel to the <1100> orientation.

FIG. 7 is cross-sectional views each showing a pn junction formed byboron ion implantation.

FIG. 8 is a perspective view and a plan view showing a MOS field effecttransistor, respectively, according to the present invention.

FIG. 9 is a perspective view and a plan view showing an insulated-gatebipolar transistor, respectively, according to the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

FIG. 2 are a perspective view of a junction-gate field effect transistoraccording to the present invention and a plan view showing only asemiconductor region. In the present embodiment, a transistor is formedon the basis of hexagonal 4H—SiC as a semiconductor material. A driftlayer 22 of high resistance n type (n-type) is provided on a siliconcarbide single crystal wafer 21 of low resistance n type (n⁺ type) byepitaxial growth. Gate layer 23 of p type is provided on part of thesurface of the drift layer by aluminum ion implantation, so that theprincipal pn junction plane, which is not in parallel to the interfacebetween the drift layer 22 and the gate layer 23, can be in parallel tothe <1120> orientation of 4H—SiC. An n⁺ type source layer 28 is providedon other part of the surface of the drift layer 22 by nitrogen ionimplantation. A source electrode 25 is through into ohmic contact withthe source layer 28, whereas a drain electrode 27 is brought into ohmiccontact with the back side of the n⁺ type water 21. Furthermore, a gateelectrode 26 is provided on the gate layer 23.

FIG. 3 is a perspective view showing the state of crystal defects in thegate layer 23 of the junction-gate field effect transistor of FIG. 2 andits plan view. In FIG. 3, the n⁺ type source layer 28, the sourceelectrode 25 and the gate electrode 26 of FIG. 2 are omitted forsimplicity.

As shown in the perspective view of FIG. 3, crystal defects 15 formed onthe crystal plane in parallel to the <1120> orientation of 4H—SiC aresmaller than crystal defects 14 formed on the crystal planeperpendicular to the <1120> orientation in the gate layer 23.Cross-sectional views of only a pn junction comprising the drift layer22 and the gate layer 23 of FIGS. 2 and 3 are shown in FIG. 4, where (a)refers to observation from the <1120> orientation of silicon carbidesingle crystal and (b) refers to observation from the <1100>orientation. To form the pn junction, a wafer of n⁺ type 4H—SiC singlecrystal is subjected to mirror polishing, and a 10 μm-thick epitaxialgrowth layer of n-type 4H—SiC is formed on the {0001} plane inclined atan angle (off-angle) of 8 degrees, followed by aluminum ion implantationas a p-type impurity down to a depth of about 0.3 μl from the surface ofthe epitaxial growth layer and then by heat treatment in an inertatmosphere at 1,700° C. for 30 minutes. Inclination at an off-angle ofthe crystal plane of single crystal wafer surface is the well known artin growth of high quality epitaxial layer with less defects and anoff-angle is appropriately selected usually from a range of one to tendegrees. In FIG. 4, crystal defects shown by black dots (14 and 15) areobservable down to about 0.3 μm in the depth direction from the surface,and the crystal defects are larger when viewed from the <1120>orientation than when viewed from the other orientation. The crystaldefects are smaller when viewed from the <1100> orientation where thecrystal plane in parallel to the <1120> orientation is observable thanwhen viewed from the other orientation. Further detailed observationmade by the present inventors revealed that such states of crystaldefects were likewise observed in case of crystal planes approximatelyin parallel to the <1120> orientation within an angle deviation of about3 degrees from the <1120> orientation.

On the other hand, as shown in the plan view of FIG. 2, the gate layer23 is in a shape of narrow stripe, whose longitudinal direction is inparallel to the <1120> orientation on the {0001} plane as the surface ofepitaxial growth layer. Thus, in the region extended in the depthdirection from the surface of the epitaxial growth layer (the side ofgate layer 23 in the perspective view) at the interfaces between thegate layer 23 and the drift layer 22, the crystal plane in parallel tothe <1120> orientation, which is along the longitudinal direction of thegate layer 23, takes a proportion of 70 to 80%. On the other hand, thecrystal plane perpendicular to the <1120> orientation is constituted bya portion of the interface, which has a curvature at the edge of thegate layer 23 in the longitudinal direction. Consequently, the crystaldefects at the pn junction in the region extended in the depth directionfrom the surface of the epitaxial growth layer at the interface betweenthe gate layer 23 and the drift layer 22 are substantially small ones.When an inverse voltage is applied to the pn junction, the leak currentcan be made smaller. Furthermore, in this embodiment, the {0001} planeas the surface of the epitaxial growth layer is in parallel to the<1120> orientation, and thus the region in parallel to the surface ofthe epitaxial growth layer at the interface between the gate layer 23and the drift layer 22 (bottom of the gate layer 23 in the perspectiveview) also forms a crystal plane inparallel to the <1120> orientation,whereby the leak current generated in the region in parallel to thesurface of the epitaxial growth layer at the interface of the gate layer23 and the drift layer 22 can be made smaller and thus the leak currentgenerated at the entirely of substantial pn junction can be reduced.

When an inverse bias voltage is applied between the source electrode 25and the gate electrode 26 of the junction-gate field effect transistorof FIG. 2, a depletion layer can be extended from the pn junction at theinterface between the gate layer 23 and the drift layer 22, therebyblocking the principal voltage applied between the drain electrode 27and the source electrode 25, where the field intensity in the depletionlayer is higher at the pn junction having a curvature than at the flatpn junction. In this embodiment, the pn junction in the laongitudinaldirection of the gate layer 23 and also at the edge in the longitudinaldirection has a curvature, and thus the field intensity can beincreased. That is, when there are large crystal defects at the pnjunction, the leak current will be increased. However, in thisembodiment, the longitudinal direction of the gate layer 23 is inparallel to the <1120> orientation, the crystal defects at the pnjunction interface having a curvature will be substantially small,giving less influences of crystal defects in the gate layer 23 upon theleak current. Furthermore, the flat region at the pn junction interfacealso forms a crystal plane in parallel to the <1120> direction, and thusthe crystal defects at the entirety of the pn junction interface will besubstantial small. That is, in this embodiment, the leak currentgenerated at the pn junction of SiC semiconductor crystal can be madesmaller.

FIG. 5 shows leak current distribution when an inverse voltage isapplied to various pn junctions formed in SiC single crystals. Case ofpn junction interface in parallel to the <1100> orientation correspondsto the pn junction comprising a gate layer 23 and a drift layer 22 in ajunction-gate field effect transistor shown in a perspective view and aplan view of FIG. 6. In FIG. 6, the gate layer 23 is formed in thedirection rotated by 90 degrees from that of FIG. 2. That is, theprincipal pn junction interface is provided in parallel to the <1100>orientation. Among cases of pn junction in parallel to the <1120>orientation, that in parallel to the <1100> orientation, and those inarbitrary orientations, the present case in parallel to the <1120>orientation has the smallest leak current.

In the embodiment of FIG. 2, the gate layer 23 is formed by aluminum ionimplantation, but can also be formed by other p-type impurity ionimplantation. FIG. 7 shows its embodiment, where a gate layer is formedby boron ion implantation. That is, FIG. 7 is cross-sectional views of apn junction comprising a gate layer 23 and a drift layer 22 in ajunction-gate field effect transistor in the same structure as that ofFIG. 2. Case of observation in the <1120> orientation of silicon carbidesingle crystal is shown by (a) and that in the <1100> orientation by(b). Procedure for forming the pn junction is substantially the same asthat of FIG. 4, but only a difference is ion implantation of boron inplace of aluminum. In FIG. 7, crystal defects shown by black dots (14)is observable down to about 0.1 μm in the depth direction from thesurface, as viewed from the <1120> orientation, but substantially not asviewed from the <1100> orientation, i.e. other orientation. That is, inplace of aluminum, even the boron can made the leak current generated atthe pn junction small. This is also applicable to other embodimentswhich follow.

In the embodiment of FIG. 5, the surface of the epitaxial layer is a{1000} plane in parallel to the <1120> orientation, but may be anothercrystal plane, because the crystal defect density derived by thealuminum ion implantation decreases inwards in the epitaxial layer inthe depth direction from the surface of the epitaxial layer, and thezone in parallel to the surface of the epitaxial layer at the pnjunction corresponds to the inner-most of the aluminum ion-implantedregion, so that the crystal defects in that zone have a lowest density,giving no substantial influence upon the leak current. Thus, even if thesurface of the epitaxial layer is another crystal plane not in parallelto the <1120> orientation in the embodiment of FIG. 5, the leak currentcan be also made smaller. This is also applicable to the aforementionedcase based on the boron ion implantation or to other embodiments whichfollow.

FIG. 8 is a perspective view showing application of the presentinvention to a MOS field effect transistor and a plan view showing onlya semiconductor region. A drift layer 22 of high resistance, n-type (n⁻type) is provided on a silicon carbide single crystal wafer 21 of lowresistance n-type (n⁺ type) by epitaxial growth. A p-type channel layer24 is provided on part of the surface of the drift layer 22 by aluminumion implantation. The channel layer 24 is in the same stripe shape asthat of the gate layer 23 in the embodiment of FIG. 2. The principal pnjunction plane, which is not in parallel to the interface between thedrift layer 22 and the channel layer 24, is formed in parallel to the<1120> orientation of 4H—SiC. An n⁺-type source layer 28 is provided onpart of the surface of the dirft layer 22 by nitrogen ion implantation.The n⁺-type source layer is brought into ohmic contact with a sourceelectrode 25, whereas the n⁺-type silicon carbide single crystal wafer21 is brought into ohmic contact with a drain electrode 27. Furthermore,a gate electrode 26 is provided on the surface of the channel layer 29through a gate insulator film 29.

In FIG. 8, when a principal voltage is applied between the drainelectrode 27 and the source electrode 25 to bring the drain electrode 27to a higher potential and when the gate electrode 26 is brought to thesame potential as that of the source electrode 25, depletion layers areextended from the pn junction interface between the channel layer 24 andthe drift layer 22 into the respective layers, thereby bringing the MOSfield effect transistor of this embodiment into a blocking state. Asalready described in detail, referring to the embodiment of FIG. 2, theregion extended in the depth direction from the surface of the epitaxialgrowth layer at the pn junction interface takes a crystal planessubstantially in parallel to the <1120> orientation in that case, andthus only substantially small defects appear. That is, the leak currentcan be reduced also in this embodiment.

FIG. 9 is a perspective view showing application of the presentinvention to an insulated-gate bipolar transistor and a plan viewshowing only a transistor region. A layer 32 of low resistance n+-typeis provided on a silicon carbide single crystal wafer 31 of lowresistance p-type (p⁺ type) and successively a layer 33 of highresistance n⁻-type thereon by epitaxial growth. A p-type layer 34 isprovided on part of the surface of the n⁻-type layer 33 by aluminum ionimplantation. The p-type layer 34 is in the same stripe shape as thoseof the gate layer and the channel layer in FIG. 2 and FIG. 8,respectively, where the principal pn junction plane, which is not inparallel to the interface between the n⁻-type layer 33 and the p-typelayer 34, is formed in the <1120> orientation of 4H—SiC. An n⁺-typelayer 35 is provided on part of the p-type layer 34 by nitrogen ionimplantation. An emitter electrode 36 is bought into ohmic contact withthe p-type layer 34 and the n⁺-type layer 35, whereas a collectorelectrode 37 is brought into ohmic contact with the p⁺-type siliconcarbide single crystal wafer 31. Furthermore, a gate electrode 38 isprovided on the surface of the p⁺-type layer 34 through a gate insulatorfilm 39.

In FIG. 9, when a principal voltage is applied between the collectorelectrode 37 and the emitter electrode 36 to bring the collectorelectrode 37 to a higher potential and when the gate electrode isbrought to the same potential as that of the emitter electrode 36 or alower potential than that of the emitter electrode 36, depletion layersare extended from the pn junction interlayer between the p-type layer 34and the n⁻-type layer 33 into the respective layers, thereby bringingthe insulated-gate bipolar transistor of this embodiment into a blockingstate. As already described in detail, referring to the embodiment ofFIG. 2, the region extended in the depth direction from the surface ofthe epitaxial growth layer at the pn junction interface takes a crystalplane substantially in parallel to the <1120> orientation in that case,and thus only substantially small defects appear. That is, the leakcurrent can be reduced also in this embodiment.

The present invention is based on a hexagonal silicon carbide singlecrystal and can reduce a leak current of a semiconductor device with apn junction and can considerably improve the reliability.

What is claimed is:
 1. A semiconductor switching device, which comprisesa silicon carbide single crystal of hexagonal symmetry having a firstconductive type and a semiconductor region having a second conductivetype opposite to the first conductive type and locating in the siliconcarbide single crystal, characterized in that a pn junction interfacebetween the silicon carbide single crystal and the semiconductor region,extended in the depth direction from the surface of the silicon carbidesingle crystal, includes a crystal plane in parallel to the <1120>orientation or approximately in parallel thereto.
 2. A semiconductorswitching device according to claim 1, characterized in that the crystalplane has a larger area than a half of the pn junction interface.
 3. Asemiconductor switching device according to claim 1, characterized inthat when the semiconductor switching device is in a principal voltageblocking state, a depletion layer is extended into the semiconductorregion from the pn junction.
 4. A semiconductor switching deviceaccording to claim 1, characterized in that the second conductive typeimpurity in the semiconductor region is introduced into the siliconcarbide single crystal by ion implantation.
 5. A semiconductor switchingdevice according to claim 1, characterized in that the surface is acrystal plane in parallel to the <1120> orientation or approximately inparallel thereto.
 6. A semiconductor switching device according to claim5, characterized in that the surface is a {0001} crystal plane or a{0001} crystal plane inclined at an angle ranging from 1 degree to 10degrees.
 7. A semiconductor switching device according to claim 5,characterized in that the semiconductor regions is in contact with thesurface and is extended in the depth direction from the surface.
 8. Asemiconductor switching device according to claim 7, characterized inthat the semiconductor region is in a stripe shape in parallel to thesurface in the longitudinal direction.
 9. A semiconductor switchingdevice according to claim 8, characterized in that the longitudinaldirection is in parallel to the <1120> orientation or approximately inparallel thereto.
 10. A semiconductor switching device according toclaim 1, characterized in that the second conductive type impurity inthe semiconductor region is aluminum or boron.